Apparatus for resetting an analog integrator

ABSTRACT

Apparatus for resetting an analog integrator with digital readout capability. The resetting signal, which discharges the integrating capacitor, is terminated when the output of the integrator reaches a level which is proportional to the analog input signal instead of completely discharging the integrating capacitor. This compensates for the errors present in prior art analog integrators caused by ignoring the analog input signal during the discharge time of the integrating capacitor. During the discharge of the integrating capacitor, an operational amplifier compares the integrator output voltage with a signal proportional to the analog input signal, called the compensating voltage. When two signals are equal the resetting signal is terminated.

United States Patent [72] inventors Lars A. Lindblad Klingen; Rune N.Kahlbom, Uplands Vasby, Sweden [2 1] Appl. No. 778,658 [22] Filed Nov.25, 1968 [45 Patented May 18, 1971 [73] Assignee Junger instrumentAktiebolag Stockholm, Sweden [54] APPARATUS FOR RESE'ITING AN ANALOGINTEGRATOR 1 Claim, 2 Drawing Figs. [52] US. Cl 328/127 [51]. lnt.Cl606g 7/18 [50] Field ofSeai-ch 307/229, 234; 328/127, 128; 235/183,150.53 [56] References Cited UNITED STATES PATENTS 3,188,455 6/1965Quick, Jr 235/183 2 cs 3 D1 L R5 RZIJFI ua 61 ca D2 "or R5 R1 u1 D3 Vin6 R12 R3 i c7 D4 R13 9 @RL R11 R10 R9 R8 3,454,886 7/1969 Bijletal3,487,204 l2/l969 Emmerich Primary Examiner-Donald D. Forrer AssistantExaminer-B. P. Davis Attamey-Fred Philpitt 328/127X 328/l27X ABSTRACT:Apparatus for resetting an analog integrator with digital readoutcapability. The resetting signal, which discharges the integratingcapacitor, is terminated when the output of the integrator reaches alevel which is proportional to the analog input signal instead ofcompletely discharging the integrating capacitor. This compensates forthe errors Blocking circuit Scoler Drive stage I Counters Patnted Mdy18, 1971 2 Sheets-Sheet 1 mm m mm 5 5 a r Patented May 18, 19713,579,125

2 Sheets-Sheet 2 Fig.2

APPAMWS W019i RESE i l G AN ANALOG HNTEGRATOR The present inventionrelates to an apparatus for resetting an analog integrator with digitalread-out of the analog signal. An automatic resetting of the integratorwill result in an extension of its range of integration in displayingthe number of resets on a mechanical or electronical counter.

Most digital readout devices are operating according to a principle inwhich the output signal of an integration amplifier is supplied to anoperational amplifier operating as a compara- A further problem in theuse of prior-art digital readout devices resides in that they disregardthe voltage being integrated overthe capacitor during its dischargetime.

The object of the present invention is to provide an apparatus forresetting an analog integrator whereby temperature drift and the maximumerror due to discharge will be substantially negligible. The inventionis mainly characterized by the fact that an operational amplifierforming part of the analog integrator is arranged to interrupt the resetcurrent through the integration capacitor as the output signal from theintegrator reaches a lower limit value corresponding to a compensationsignal which is directly proportional to the analog input signal at thetripping instant of the reset current.

One embodiment of the apparatus according to the invention will now bedescribed more in detail reference being made to the accompanyingdrawings' FIG. 11 shows a block diagram of an analog integratoraccording to the present invention, and

FIG. 2 shows a waveform diagram illustrating the functions of thevarious blocks of HG. l.

An input voltage V, is integrated by means of a resistor R and acapacitor C as well as an operational amplifier U1. The output of theintegrator will then have a polarity opposite to that of the inputvoltage V,,,. The integrator Ul is capable of integating' both positiveand negative input voltages without the need of any switching operation.la the present example, a positive input voltage V is chosen. In thiscase, the output voltage V derived from the integration amplifier Ulwill rise at a rate which depends on the resistance R and capacitanceC,. A plurality of operational amplifiers U2, U3 and U4 are coupled ascomparators which means that they will emit a voltage pulse when thevoltage supplied adopts a certain predetermined value. The switchinglevel of operational amplifiers U2 and U3 is determined by a voltagedivider R8, R9, RM) and Rl ii. if, as assumed hereabove the analog inputsignal V is positive, thenthe output voltage V adopts apredeterminedlevel, such as 5 volts, for example, the comparator U2 will switch over,whereby a positive voltage pulse V, will appear at the output of thecomparator. This voltage pulse is differentiated by a capacitor C5 and aresistor R5, thus resulting in a positive and a negative pulse. A diodeD1 will only admit the positive pulse therethrough to be supplied to aflip-flop U6. The latter will then be reversed and emit a positivesignal to the minus-input-terminal of an operational amplifier U5. Theoutput voltage of this last-mentioned amplifier will then be negativeand fed back through a resistor R2 to the input of integration amplifierUl. This will cause the integration capacitor Cl to discharge at a ratedepending on the values of resistor R2 and capacitor Cl. The dischargeperiod of the capacitor is selected to be approximately 100 timesshorter than the maximum integration time period.

Now, according to the invention, an operational amplifier U4 has beenincorporated in the analog integrator. The input voltage of thisamplifier U4 is directly proportional to the input voltage V, of theintegrator U1 and will here be designated V-compensation (V At thebeginning of the reset current, the output voltage V of the integratoris 5 volts and the voltage V is directly proportional to the inputvoltage V,,,. The reset current, having negative polarity, willdischarge capacitor C1, and when the output voltage V has declined to avalue equal to the voltage V the comparator U4 will emit a negativevoltage pulse V,,. This negative voltage pulse is differentiated by acapacitor C7 and a resistor R7. A diode D3 will only admit the negativepulse to pass which is then reversed in polarity and supplied toflip-flop U6 causing resetting of the latter. This will causeinterruption of the resetting current through capacitor C l.

A similar lapse will be repeated, if the input voltage V is negative.The only dilTerence will be that the operational amplifier U3 willinstead function as a comparator, and the output signal from a flip-flopU7 will release the resetting current, being positive since theinput-voltage is negative. Consequently, comparator U4 will emit .apositive voltage pulse when the resetting current is to be interrupted.This positive voltage pulse resets flip-flop U7 which, in its turn,interrupts the resetting current. Thus, depending on the polarity of theinput signal, either comparator U2 or comparator U3 will release theresetting current, which, however, in both cases is being interrupted byimpulses from. comparator U4. Connected between amplifier U5 andresistor R2 is a blocking circuit preventing leakage current to flowthrough resistor R2 during the integration period. Recording of theresets may be effected by supplying the output signal of operationalamplifier U5, in addition, to a sealer or a counter recording the numberof discharges.

The progress so far described will now be explained with reference tothe waveform diagram of FIG. 2.

The output voltage V from the integration amplifier U1 is represented bycurve 1, and at the value 5 volts a positive voltage pulse V, is emittedby comparator U2, as shown in curve 2. The voltage pulse isdifferentiated, as appears from curve 3. The negative pulseis suppressedby a diode, and the positive pulse according to curve 4 is supplied tothe input of operational amplifier U5. The operational amplifier US willthen emit a negative reset current, the corresponding voltagecharacteristic of which is represented by curve 10, thereby causingcapacitor C1 to discharge, as appears from curve 1. When the voltageaccording to curve l has declined to a level corresponding to V anegative: voltage pulse will be emitted by comparator U4 according tocurve 6. This negative voltage pulse is differentiated, as appears fromcurve 7. The positive pulse is suppressed, as appears from curve 8, andthe negative pulse is finally reversed in polarity, as appears fromcurve 9. The last-mentioned polarity-reversed pulse resets the flip-flopU6, thereby interrupting the resetting current as appears from curvell), after which the integration cycle can be repeated.

it is seen from the foregoing description that the maximum error in thedigital read-out apparatus will appear when the voltage V equals zero,which means that the reset current will cause a complete discharge ofthe capacitor. Thus, if no voltage V existed, this would mean that thevoltage inte'grated over the capacitor C 1 during its discharge time wasnot taken into consideration. On the other hand, if the voltage V isintroduced, compensation will be obtained for the voltage integratedduring the discharge time of the capacitor. The voltage V can beselected to give satisfactory linearity. The method has certainly itslimitation, for instance where the input voltage V exhibits rapidvariations, in which case the error may rise to a maximum of 1 percent,corresponding to the zero-value of the voltage V In most cases, however,the signal to be integrated has sufficiently slow-rate variations tomake the error completely negligible. However, if rapid events are to beintegrated, it would be suitable to introduce an integration or delay ofthe compensation voltage V The most significant advantage of theinvention resides in that 3 extended-time drift and temperature driftwill become substantially negligible.

We claim: I

signal, a resetting signal for feeding back into the input of saidintegration amplifier at a polarity opposite to that of the input signalto cause discharge of said integration capacitor connected to saidinput, in which apparatus a second operational amplifier forming a partof said analog integrator is arranged to interrupt said resetting signalwhen the output signal of said integration amplifier reaches its lowerlimit value corresponding to a compensation signal which is directlyproportional to said input signal during the occurrence of saidresetting signal.

1. Apparatus for resetting an analog integrator providing digitalreadout of an analog signal, such digital integrator comprising anoperational amplifier, including an integrating capacitor, arranged tooperate as an integration amplifier to convert an analog input signalinto an output signal varying between two limit values and meansresponsive to the output signal for initiating, at the upper limit valueof said output signal, a resetting signal for feeding back into theinput of said integration amplifier at a polarity opposite to that ofthe input signal to cause discharge of said integration capacitorconnected to said input, in which apparatus a second operationalamplifier forming a part of said analog integrator is arranged tointerrupt said resetting signal when the output signal of saidintegration amplifier reaches its lower limit value corresponding to acompensation signal which is directly proportional to said input signalduring the occurrence of said resetting signal.